The present invention is in the field of integrated circuit devices and more particularly is directed to digital-analog multipliers.
In the prior art, multiplier circuits have generally been provided by signal transformations in the current domain, i.e. by controlling sums of weighted current signals.
In one form, multiplying digital-to-analog converter devices have been produced using bucket brigade devices (BBD's). These converter devices generally utilize a set of binary-weighted capacitors which have an analog signal impressed across them. MOS transistors drive currents into and out of selected ones of the set of capacitors. Control of the particular ones of the set of capacitors which are so driven, is established by gates which are controlled by a digital word signal (which may be user-controlled for a variable multiplier, or may be preset for a fixed weight multiplier). The charging or discharging currents for the capacitors are summed and serve to launch a charge packet in a BBD. While that resultant charge packet in the BBD is proportional to the product of a digital word (which controls the gates to the respective capacitors) and an analog voltage applied to those capacitors, the generation of this charge packet is relatively slow, principally due to the long time constant associated with the MOS transistors used in the charging of the capacitors.
It is an object of the present invention to provide an improved digital-analog multiplier.
Another object is to provide an improved multiplying digital-to-analog converter (MDAC).
It is another object to provide an MDAC which is characterized by the relatively high speed and relatively low power operation.